1. Field of Invention
The present invention relates to an interface for a memory array, and more specifically to an asynchronously operating configurable memory interface for a static random access memory (RAM).
2. Description of the Prior Art
Static random access memories, because they do not need to be periodically refreshed, in contrast to dynamic random access memories, can be operated asynchronously, which can increase their speed.
Furthermore, dual ported static RAMS are known, which allow more than one microprocessor to simultaneously access the same memory. However, these dual ported static RAMS are very expensive.
Given these considerations, it is known to try and use a less costly interface that is attached between two processors and the static RAM to closely simulate simultaneous access of the static RAM. However, these known interfaces also have disadvantages. One of these disadvantages include the use of a common buss between the processors and the interface, which slows down the processors. The lack of configurability when prioritizing which processor should gain access to the static RAM when more than processor simultaneously attempts to access the static RAM for a memory operation is another problem, as well as the lack of configurability with respect to word and data widths.
As such, a new type of configurable interface is needed.